The algorithms of inserting boundary-scan circuit automatically

Boundary Scan is one of the most popular technique of DFT (Design For Testability) today. Although some tools can automatically insert and verify boundary-scan circuitry, but they are not easily used. So we designed a set of tools. The tool set can process the RTL and behavioral VHDL files, distinguish the source files with boundary-scan circuitry, generate VHDL with IEEE 1149.1 compliant boundary scan circuitry. This paper describes the main algorithms of boundary-scan in detail. First the tools scan the VHDL source code and obtain the pin and the pin types. Next they consider the bidirectional signal, a 3-state signal which controlled pins BSCs (boundary-scan calls) configuration and process the clock pin. Finally, the corresponding VHDL and BSDL files and test bench files with IEEE defined basic instructions, are generated.