Post-deposition annealing and thermal stability of integrated self-aligned E/D-mode n++GaN/InAlN/AlN/GaN MOS HEMTs

We describe technology and evaluate thermal performance of enhancement/depletion (E/D)-mode n
⁺⁺
GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate processing, where n
⁺⁺
GaN layer was etched away only under the gate for E-mode and for D-mode stay intact. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Threshold voltage of the as deposited E- and D-mode HEMTs was +0.6 V and −2.4 V, respectively. After post-deposition annealing (PDA) at 300 °C in N
2
atmosphere the threshold voltage has been changed to +3 V and − 4,4 V for E- and D-mode HEMTs, respectively. These effects were explained by decreasing density of deep interface states in the D-mode HEMTs and decreasing surface donors at the semiconductor-oxide interface in case of the E-mode HEMTs. After PDA, electrical performance of both types of transistors was evaluated from room temperature to 150 °C. At elevated temperatures, injection and trapping of electrons from the gate metal to the oxide was found in D-mode HEMTs, while emission of electrons from the oxide-semiconductor interface states was crucial for the E-mode ones.