Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation

In this chapter, a novel device structure for a gate‐on‐germanium source (GoGeS) tunnel field‐effect transistor (TFET) on a bulk silicon substrate is proposed for sub‐0.5 V operation. Tunneling in line with the gate electric field, which increases the effective tunneling area and, hence, the ON‐state current
I_ON
, is achieved in this device by constructing its gate on the germanium source region. To improve the subthreshold swing (
SS
), lateral carrier tunneling is eliminated by carefully designing the device structure. The use of a small gate‐to‐channel overlap results in reduced fringing‐induced barrier lowering at the gate edge that further improves the
SS
and
I_ON
of the device. The spreading of the fringing electric field is also reduced by employing a step in the silicon channel region, which again improves both
SS
and
I_ON
. As a result of all these, supersteep
SS
and high
I_ON
are achieved, enabling sub‐0.5 V operation of the proposed gate‐on germanium source tunnel field‐effect transistor (GoGeS TFET).