Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations

CORDIC based cascade orthogonal IIR digital filters have sharp transition band and exhibit low sensitivity in both the pass band and stop band which are suitable for VLSI implementations. However, the achievable sample rate of these filters is limited due to the presence of feedback loops. To overcome the speed limitation and achieve high-speed/low-power implementations, a novel algorithm transformation technique is proposed based on retiming and orthogonal matrix decomposition techniques which can increase the maximum filter sample rate to /spl Oscr/(1) level which is independent of the filter order. The proposed parallel and pipelined architectures consist of only Givens rotations which can be mapped onto CORDIC arithmetic based processors.