Power reduction through iterative gate sizing and voltage scaling

The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. An iterative framework is proposed to integrate voltage scaling with a min-separator based gate sizing to enhance power saving. The proposed methods are evaluated using the MCNC benchmark circuits. An average of 19.12% power reduction over the circuits having only one supply voltage has been achieved.