Efficient 6-bit A/D converter using a 1-bit folding front end

An efficient analog-to-digital (A/D) converter architecture that uses a 1-bit folding front end is described. The folder is realized using a zero-crossing detector and transmission gates. The problem arising from the nonideality of the folding operation is handled in a special way. The use of a single folder in front rather than the conventional approach of using multiple folders results in a significantly smaller input capacitance. The architecture has been used for realizing a 7S-Msamples/s, 6-bit A/D converter for local-area-network application. The prototype has been implemented in a 0.5-/spl mu/m single-poly, triple-metal digital CMOS technology. It occupies an area of 1 mm/sup 2/ and has a power consumption of 110 mW from a 3.3-V supply.