4-channel rad-hard delay generation ASIC with 1 ns timing resolution for LHC

An ASIC was developed to precisely delay digital signals within the range of 0-24 ns in steps of 1 ns. To obtain well defined delay values independent of variations in process, supply voltage and temperature, four independent delay channels are controlled by a common control voltage derived from a delay-locked loop (DLL), which is synchronized to an external 40 MHz clock signal. The delay values of the four signal channels and the clock channel can be individually programmed via an I/sup 2/C interface. Due to an automatic reset logic the chip does not need an external reset signal. A first version of the chip was developed in a non-rad-hard 0.8 /spl mu/m technology and the successful prototype was then transferred to a radiation hard process (DMILL). Measurement results for both chip variants will be presented.