A Low-stress Trench Isolation Structure And Its Electrical Characteristics Of Sub 20 Ps High-speed ECL

This paper presents a low-stress trench isolation structure to realize very small parasitic capacitances for sub 20 ps ECL circuit. We will show that, even using 0.8 pm design rule and relatively low fT value of 20 GHz, comparable delay time with that by 40 - 50 GHz fT can be achieved.