Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems

This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r=1/3 and the constraint length K=9 (256 states). This chip has been implemented using 0.5 /spl mu/m three-layer metal CMOS technology and is targeted for high speed convolutional decoding for next generation wireless applications such as wide-band CDMA mobile systems and wireless ATM LANs. The chip is expected to operate at 20 Mbps under 3.3 V and at 2 Mbps under 1.8 V. The add-compare-select (ACS) units have been designed using bit-serial arithmetic, which has made it feasible to execute 256 ACS operations in parallel. For trace-back operations, we have developed a novel power-efficient trace-back scheme and an application-specific memory, which was designed considering that 256 bits should be written simultaneously for write operations but only one bit needs to be accessed for read operations. We have estimated that the chip dissipates only 10 mW at 2 Mbps operation under 1.8 V.