Drain-offset ZnO thin film transistors for high voltage operations

We report ZnO thin film transistors (TFTs) with offset drain for high voltage operation. Offset-drain FETs using Si, a-Si:H, and pentacene have been previously demonstrated [1,2,3]. The TFTs use a bottom gate structure with Al
₂
O
₃
gate dielectric and ZnO active layers deposited by plasma enhanced atomic layer deposition (PEALD). As the drain offset is increased from 0 μm to 2 μm· the drain-to-source breakdown voltage increased from 33 V to 82 V, while the linear mobility decreased from 10 cm
²
/Vs to 4 cm
²
/Vs. Our process flow is simple and compatible with glass and polymeric substrates.