High-speed FPGA implementations of Volterra DFEs based on iterated short convolution

In this work, an architecture of low complexity non-linear Decision Feedback Equalizers is proposed, where the parallel filters of the feed-forward section are hardware-efficient structures based on Iterated Short Convolution. For the design of the parallel filters an algorithm is proposed, which provides an architecture with regularity that is more suitable for FPGA implementation. The proposed architecture achieves the typical throughput of 10 Gb/s, while its balanced design allows the implementation on smaller FPGA devices while reaching the target throughput.