Junctionless Array with Ultrathin Poly\TiN Floating Gate and HfAlO Based Intergate Dielectric for Sub-15nm Planar NAND Flash

We look at the challenges for scaling planar NAND flash for sub-15nm nodes, and show the implementation of hybrid poly\metal floating gate (FG), HfAlO based IGD, junctionless array, WL trimming, and EUV spacer defined double patterning in a fully planar NAND Flash array with good programming performance.