An Efficient FPGA Implementation of a Quadrature Signal-Generation Subsystem in SRF PLLs in Single-Phase PFCs

Synchronization with the utility voltage is naturally carried out by a diode bridge stage in single-phase active rectifiers, while an active synchronization is included in the control algorithms applied to modern bridgeless topologies. Sensorless line current rebuilding algorithms also need synchronization with the line voltage to compensate at least for part of the current estimation error. The phase-locked-loop (PLL) circuits employed in single-phase ac-dc converters are reviewed and a new digital PLL algorithm, based on the synchronous reference frame, is proposed. It is implemented in a field-programmable gate array to utilize the parallelism and superior time resolution. Considering a restricted frequency variation of the line voltage around the central frequency, the orthogonal signal is obtained by a discrete differential operator designed to ensure unity gain at the central frequency. Its performance, including the memory and computational cost, versus previously consolidated algorithms implemented in the same device is analyzed. Simulations and experimental results prove its suitable behavior in steady state at different line frequencies and under line voltage and frequency transients.