Frequency Domain FIR filter optimization for multi-core C6678 DSP

This paper is focused on the optimal utilization of hardware resources within a processor during the execution of desired source codes. As an example, the algorithm which is commonly used for performance benchmarks was applied. In this paper we optimize the signal processing algorithm, FDFIR (Frequency Domain FIR filter) for the specific architecture of the eight-core digital signal processor TMS320C6678. This algorithm is suitable for benchmarking because it contains both forward and inverse Fast Fourier Transform and vector multiplication as well. The goal of the analysis is to describe and avoid any idle operations in the algorithm which extend the computational time and increase the power consumption of the processor. The proposed approaches were explained in detail for a test case with a very short vector length.