Management of multiple-pass constraints [IC fabrication]

The theory of constraints (TOC) is becoming a new paradigm in the semiconductor industry. Most practical uses of TOC are for bottlenecks with only one visit to the fabrication process such as typical job shop linear lines. Applying TOC to constraints with multiple steps has been shown to be too complex to handle a semiconductor shop-floor. This restriction to constraints with only one visit limits TOC potential in semiconductor environments. In this paper, we present a methodology developed to allow for the use of the TOC philosophy in fab lines with more than one product flow and more than one visit to the bottleneck in each product flow. This method consists of dividing each process sequence in segments, where each segment finishes in one visit to the bottleneck and has only that single visit to the bottleneck. Once the capacity of the bottleneck is split between the visits, each segment is managed as an independent line. The method is suitable to be used in a production environment on a shift to shift basis and allows throughput optimization of real bottlenecks.