Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor

A determinant computing circuit in floating point format has been designed and tested for use in a CMOS ASIC acoustic localization processor. The Internal Division Method (IDM) was used to implement the operation, employing a modified SRT radix-4 circuit for division operations. The unit was designed for VLSI implementation in a commercial 130 nm low-power CMOS process, with an operation frequency of 100 MHz. The algorithm employed is parallelizable for future prototypes, should a higher operation frequency be required.