Implementation and performance analyses of a novel optimized NoC router

Technology scaling has led to the integration of many cores into a single chip. Multiprocessor Network-on-Chip (NoC) seems to be a good solution for the higher performance desired VLSI designs. The main challenge is how to enhance the communication efficiency in NoC. The NoC is a new paradigm which is fast emerging at present. The performance of the on-chip-networking depends on routing techniques used in the system. The existing techniques such as Round Robin Arbitration are not so efficient in finding an optimal path. The authors have chosen a different routing algorithm called Optimal Address Based Router (OAR) to find an optimal path which has low overhead. In this paper, we have reported a comparative evaluation of Optimal Address Based NoC router and Round Robin Arbitration based NoC router. The simulated results indicate that the Optimal Address Based NoC router is a better choice. The implementation is done on FPGA Spartan 3Xc 3s400 board. Further analyses of results shows that the optimal address based router consumes 71% lower power, occupies 90% less area and is faster by a factor of 35%.