Determination of Source-and-Drain Series Resistance in 16-nm-Gate FinFET Devices

Source/drain (S/D) series resistance is difficult to extract, owing to poor epigrowth and nonuniform distribution of current density in S/D, critical limitation of restrictive design rule, ultrathin contact film, and complicated 3-D FinFET structure. In this brief, we, for the first time, propose a novel test structure for the measurement of the S/D series resistance. This technique enables us to determine the individual value of the S/D series resistance resulting from the S/D contact, the S/D epigrowth fin, and the channel gate, respectively. Each device's S/D series resistance on different layout locations is characterized on the basis of its connection with specified S/D contact. The test structure and extraction method can be applied to monitor the process development of sub-16-nm-gate multifin bulk FinFET devices, such as the channel fin doping, the S/D epigrowth, and the S/D contact size formation.