Design and implementation of parallel multi-access memory interface

In Multi-processor Systems on Chip (MPSoC), data interacts frequently between processors and off-chip memory. Higher bandwidth utilization of memory interface (MI) is needed urgently by parallel multi-tasks in MPSoC. Referring to the multi-process time-shared scheduling algorithm of CPU, this paper discusses a parallel multi-access technique on user side which applies to MPSoC. This technique utilizes the bandwidth distinction between both sides of the MI and time slice concept to achieve time-shared exclusive operation on SDRAM side and parallel operation on user side. The mechanism of self-inquiry and allocation of data port (SIADP) is added to allocate data port automatically in order to solve the problem of allocation in parallel multi-access. Time slice round robin mechanism is optimized to hide data channels switching time to achieve seamless switching on SDRAM side. With above studies, this paper designs a kind of parallel Multi-Access Memory Interface (MAMI) supporting three read and three write operations and implements it on FPGA. Four different sizes of data transmission have been tested on MAMI hardware prototype. The verification results show that, the highest Data Transmission Parallelism (DTP) is above 5.5 and the average of DTP is more than 5.