Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Chip-Package Interaction (CPI) related failure risk has increased in organic laminate-based electronic packages fueled in part by certain industry-segments' requirements for larger silicon die size and signal performance. CPI-related stresses increase directly with radial distance from the center of the die, known as distance from the neutral-point (DNP). The resulting risk of local delamination (White Bumps, WBs) in the silicon back-end-of-line (BEOL), fracture of C4 interconnections and failure of underfill and chip ultimately impact electronic package reliability. Named from the notable visible white halo or circle around a C4 in a CSAM (C-Mode Scanning Acoustic Microscopy) image, WBs are the prime indicator of a CPI-related failure event in an organic laminate-based electronic package. Laminate and BEOL design, specifically wiring proximal to the C4 interconnection, are known to influence WB reliability. In this paper we specifically study the effect of laminate and BEOL design on the generation of white bumps. Four different chip designs, some of which are more susceptible to WBs than others are mated with both product-design and "flat" laminates, or laminates consisting of only a core and single copper layer on each side. Our ultimate goal is to highlight the silicon & laminate designs' ability to modulate WB occurrences, to create design ground-rules thereby relaxing the cost and facilitating the development of package assembly solutions. A comprehensive experiment was carried out to achieve these goals. As companion test vehicles to product laminates, four different flat laminate (0-2-0) designs were fabricated with several different core materials to both segregate the effect of laminate wiring design and modulate the overall laminate coefficient of thermal expansion (CTE). Four separate chip designs were used to study the effect of the back end of line design. Thermal stress was induced in the experiment using a high-cooling rate or "hammer" chip-join (HCJ) reflow profile which drives a higher C4 shearing stress than with the nominal profile. The occurrence of WBs was then monitored while the test vehicles were repeatedly subjected to the hammer profile in a controlled hammer thermal cycling (HTC) process. Diagnostic measurements including 3D Surface Metrology and CSAM were performed after each HTC cycle to monitor both laminate warpage and WB occurrence respectively. White Bump evolution was statistically analyzed and correlated to each die design, laminate cross-sectional design and CTE. Results demonstrated the importance of laminate design in that the flat laminates consistently lead to fewer WBs than product laminates. Lower-CTE laminates also result in fewer WBs than product laminates.