A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells

Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. Triple-threshold-voltage seven-transistor (7T), eight-transistor (8T), and nine-transistor (9T) SRAM cells are characterized for layout area, data stability, write voltage margin, idle mode leakage currents, data access speed, and active power consumption considering process parameter fluctuations in a TSMC 65 nm CMOS technology in this paper. The single-ended and differential read / write schemes are also compared for data access speed and power consumption in SRAM circuits.