A new current mode programmable cellular neural network

We report on the design of a full-analog current-mode CNN in a 1.2 /spl mu/m CMOS technology, whose cell core is characterized by an intrinsic capability of weights control, low power consumption and small area occupation. Circuit simulations allowed the design approach to be validated and the electrical performance of the CNN to be predicted; moreover, it is shown that the proposed CNN can be successfully adopted for several applications in image processing. A preliminary CNN test-chip consisting of a 8/spl times/1 array for connected component detection and shadow detection, is currently being fabricated at IRST (Trento Italy) in a 2.5 /spl mu/m CMOS technology.