Time memory cell VLSI for the PHENIX drift chamber

A high-precision time-to-digital-converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 /spl mu/sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 /spl mu/m CMOS gate-array technology.