Board level reliability comparison of Bump on Polymer WLCSP structures

There are different types of Wafer Level Chip Scale Package (WLCSP) design in high volume production today, with specific design approaches used in different applications. Among the WLCSP variants, Bump On Polymer (BOP) WLCSP is the most widely used and currently accounts for more than 70% of WLCSP production. There are a number of design guidelines that are recognized to improve Board Level Reliability (BLR) for WLCSP packages e.g. smaller die size, and larger solder joint size (larger solder ball pitch). However, the move to advanced wafer nodes and increasing functionality, along with the pressure to reduce costs, restricts the design freedom for the WLCSP device. Traditional BOP WLCSP designs use 4 layers: Polymer-1, Redistribution metal (RDL), Polymer-2, under bump metallization (UBM). But by careful selection of the polymer and RDL designs and materials, BOP WLCSP devices can be designed with the UBM layer omitted. In the case of this 3-mask BOP WLCSP the solder ball/bump is attached directly to the RDL. However, the omission of the UBM layer changes the way that the BLR stresses are transmitted from the solder ball/bump to the WLCSP RDL and polymer layers. In order to establish the design rules for the 3-mask BOP WLCSP it is very important to understand the BLR performance for different design options. In this study, we will compare the BLR performance of 3-mask BOP WLCSP designs with 4-mask BOP WLCSP, including the analysis of the critical design features for the 3-mask BOP WLCSP.