Performance analysis of cosimulating processor core in VHDL and SystemC

Advances in SoC design complexities require newer methodologies and tools. Traditional RTL-level approach has become a bottleneck, resulting in emergence and standardization of SystemC as a design-language. IP design-houses are interested in providing SystemC models of their portfolio IPs, despite already existing VHDL views. This paper describes a methodology to translate existing VHDL IPs to SystemC, ensuring correctness, quality as well as maintainability of the translated code. The standard practice is to translate a subset of IPs at a time and cosimulate with the rest of the system to validate the translated IPs. Hence, this paper explores scenarios that affect the cosimulation performance. Varying cosimulation scenarios affect the performance upto 30%. Both the contributions of this paper, translation methodology and the cosimulation performance-analysis are relevant to a wider SystemC community, including designers and architects. Furthermore, the results can be used for optimizing cosimulation tools as well system-level-models.