A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS

A 64-way time-interleaved successive approximation based ADC front-end efficiently incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits peak ENOB at a 10GS/s sampling rate. Fabricated in 1.1V 65nm CMOS, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33mm
²
core ADC area.