Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance

Switching speed, power consumption, standby leakage current, and silicon area are major concerns in buffer design. A novel dual-threshold-voltage buffer is proposed in this paper for higher energy efficiency and shorter propagation delay while driving high capacitive load. The novel buffer offers up to 23.3% shorter propagation delay, 13.6% less switching energy consumption, and 75.7% lower standby leakage current as compared to the conventional drivers under equal silicon area and identical extrinsic load capacitance conditions in a TSMC 65nm multi-threshold-voltage CMOS technology.