Testing of a low-VMIN data-aware dynamic-supply 8T SRAM

Due to the demand of lower power, a lot of research effort has been devoted into developing new SRAM cell designs that can operate with low supply voltage. The new SRAM cell designs have their own cell structures and design techniques, which may result in different faulty behaviors than the conventional 6T SRAM. Accordingly, specialized test methods are usually required for the uncovered faults of traditional tests. In this paper, we focus on testing open defects in a new low-V
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data-aware dynamic-supply 8T SRAM design. The new SRAM utilizes a data-aware dynamic-supply circuitry cooperating with two write-word-lines to assist the write and an independent read path to enhance the read-SNM. Based on the specific cell structure, we propose a novel test method for the open defects. The test method creates an in-cell self-attacking environment and can detect all the defects undetected by traditional tests in both the SRAM cell and the data-aware dynamic-supply circuitry. Also, the method requires much less test time when being compared to the traditional floating bit-line attacking method.