Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

A digitizer designed to read out column-parallel charge-coupled devices used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined analog-to-digital converter and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The analog-to-digital converter multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the imager. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The analog-to-digital converter exhibits 188
$\mu$
V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65-nm CMOS process. The digitizer will be applied to the development of a proof-of-principle 2D, 10 Gigapixel/s X-ray detector.