A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links

A novel phase rotating PLL with a dual phase frequency detector (PFD) for 5Gb/s serial links is proposed. By employing a PFD controller, the PLL eliminates a fatal error in phase interpolation due to a nondeterministic characteristic of the PFD. It achieves interpolation between two clocks spaced 180° apart, making the overall structure much simpler with low power consumption. The test chip was implemented in a 65-nm CMOS technology. 8 multi-phase clocks can be simultaneously shifted in steps of 25ps, showing both INL and DNL less than half LSB. Its rms jitter is 0.18ps at 1.25GHz and power consumption is only 3mW from a 1.2V power supply.