Fast VLSI binary addition

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt/sub fa/ to Wt/sub mux/ where t/sub fa/ and t/sub mux/, respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W, is a power of two, then all carry signals can be generated in log/sub 2/Wt/sub max/ time using W(log/sub 2/W-1)+1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog/sub 2/W+1) multiplexers in time (log/sub 2/W+1)t/sub max/. If the specified converter latency is greater than log/sub 2/W/sub mux/, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder.