High performance JPEG decoder based on FPGA

This paper describes designing a realtime Joint Photographic Experts Group (JPEG) decoder which is capable of high definition images decoding and realized in a Xilinx Vertex 5 Field Programmable Gate Array (FPGA). We propose a highly efficient pipelining FPGA implementation of the two-dimensional inverse discrete cosine transformation. Ping-pong buffer is introduced in order to improve decoding performance. This JPEG decoder IP performs decompression of 1920 × 1080 pixels images with a speed of 30 frames per second at a required operating frequency as low as 100 MHz.