A 4-channel analog front end for 25.6 Mbps ATM switches

This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels.