Clock-jitter sensitivity reduction in CT ΣΔ modulators using voltage-crossing detection DAC

A fixed-pulse shape current steering feedback DAC for reducing the clock-jitter sensitivity in CT ΣΔ modulators is presented. Comparing with traditional solutions for clock-jitter effect reduction, the proposed technique uses fixed-pulse shape feedback to achieve higher feedback precision. By applying voltage-crossing detection, fixed-shape feedback pulse with immunity to clock-jitter influence can be generated. A self-reset zero-crossing detector was also designed to reduce the power consumption. The proposed feedback DAC was verified in the design of a 2
^nd
order, 1-bit CT ΣΔ modulator. Full transistor level simulation results show that a 62.5dB SNDR can be achieved with a clock-jitter not larger than 5%TS. In contrast with the utilization of a general RZ feedback DAC, the proposed technique improves the SNDR by 35dB under 5%TS of clock-jitter effect.