Parasitic resistance reduction technology

We reported double-gate transistors with reduced source-drain (SD) resistance with aluminum (Al) implant on S/D for sub 22 nm technology node. Al implanted S/D can provide to modulate the electron barrier height of PtSi towards the conduction band. We also investigate Schottky barrier modulation using a new Ge ion implantation (I/I) and segregation approach and the impact of spike anneal on the SBH tuning. Novel silcide alloys of Ni with Yb or Er can be adopted for a FinFET structure. These techniques attribute constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.