A delay model allowing nano-CMOS standard cells statistical simulation at the logic level

In nano-scale digital CMOS ICs, technology parameter variation limits the usefulness of traditional corner-based timing simulation in favor of statistical simulation. Yet, logic level delay modeling featuring technology variation aware timing is an open challenge. We present a new semi-empirical delay model of digital CMOS cells, accounting for input slope and technology parameters, featuring Spice-level accuracy and full suitability for logic level (i.e. fast) statistical timing simulation in an HDL environment. The approach has been tested against Spice BSIM4 targeting a library of 272 standard cells.