A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation

This paper presents the design of a 1 GHz Delay-Locked Loop (DLL) with embedded phase interpolation. The DLL was designed in a 0.13μm SiGe BiCMOS process and provides a measured single-tap phase range of 50ps (18°) with an average and worst-case phase resolution of 1.36ps (0.49°) and 5ps (1.8°), respectively. This translates to beamsteering resolutions of <; 3.5mm in free space when integrated into mm-wave imagers that utilize time-domain beamforming. The DLL has an average output rms-jitter (across all interpolation steps) of 860fs. The DLL consumes 33 mW of power and occupies an area of 0.185mm
²
.