High speed frequency synthesizer based on PLL

A new frequency synthesis technique is proposed that eliminates trade-off dilemma between small settling time and good resolution, ideal for fast frequency hopping systems. The frequency synthesizer is based on a PLL that employs a digital phase accumulator that has the property to calculate the phase difference of the two different input frequencies (reference frequency and output frequency), at the maximum possible rate. This digital phase accumulator normalizes the phase increments of the two input frequencies by multiplying the phase, instead of dividing the frequency, as done in the traditional PLL based frequency synthesizer. Therefore, the sampling rate of the phase of each frequency is not reduced down to the step frequency of the synthesizer, but is as high as the reference and the output frequencies. This results in an output from the digital phase accumulator which has harmonics at high frequencies which can be cut-off by a wide bandwidth LPF. As a result, the settling time of the synthesizer is independent of the frequency step, corresponding to the resolution, and can be reduced dramatically compared to the settling time achieved by a high resolution ordinary PLL based frequency synthesizer.