Formalization of confidence levels in verification efforts

In the present day, program codes that are written in Hardware Description Languages such as Verilog and VHDL, are very complex that includes numerous state spaces, larger set of inputs and as many outputs to the system. The verification space is almost infinite over complex circuit designs written using these HDLs, and hence functional verification is seldom complete. For a given design, the confidence levels quoted by the verification engineers today is rather an estimate than being the actual number. It is quite impossible to put a percentage of confidence on these verification levels. This paper presents a methodology to formalize an equation to present a percentage of confidence level in verification for combinational logic. Arithmetic for single precision floating type numbers is presented as an example to apply the equation and present its percentage of confidence level during its verification.