Abstract:
This paper represents a new self timed signaling technique for low power SerDes transceiver. A three level coding technique enables extracting the clock from the data usi...Show MoreMetadata
Abstract:
This paper represents a new self timed signaling technique for low power SerDes transceiver. A three level coding technique enables extracting the clock from the data using simple phase detector rather than using complex power hungry blocks such as Clock Data Recovery (CDR) or a Phase Locked Loop (PLL). This SerDes transceiver was implemented using 90nm TSMC technology. The transmitter serializes 8 parallel bits at 1.125GHz, and multiplexes the 10Gbps serial data stream with a 20GHz clock on a single line using three level signaling. The total power consumed in the Tx/Rx pair with the transmission line is 15 mWatt, which is very small as compared to other conventional architectures.
Published in: 2010 International Conference on Energy Aware Computing
Date of Conference: 16-18 December 2010
Date Added to IEEE Xplore: 28 January 2011
ISBN Information:
Print ISSN: 2381-0947