FPGA-based multi-channel CRC generator implementation

This article mainly describes a way of designing a parallel and highly pipelined Cyclic Redundancy Code (CRC) generator. The design can handle five different channels at an input rate of 2Gbps each. The generated CRCS are compatible with the 32-bit Ethernet standards. This circuit has been implemented with the chip EP2C35F672C6 of ALTERA using the properties of Galois Field. The synthesis results show that the design can meet the needs of high-speed data integrity check.