Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures

In this paper we evaluate the compromising effect of energy saving and throughput degradation on a fully asynchronous NoC architecture with regards to the dynamic voltage scaling guidelines. The investigated fully asynchronous NoC architecture is suitable for GALS-based MPSoCs architectures. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations, where the energy/throughput trade-off is reported and analyzed. Our results indicate that, although lower power may also be achieved by dynamic throughput scaling, this technique yields negligible energy saving for our asynchronous NoC. Therefore, we suggest a dynamic voltage scaling for this architecture which can save 40% energy at the expense of 13% throughput degradation.