Silicon Bipolar Demultiplexer/Decision Circuit for Gigabit Optical Communication Systems

A silicon bipolar IC for the receiving end of a gigabit fiber optic trunk line is presented, performing both demultiplexing and decision functions. The circuit is based on a 2 μm non-self-aligned silicon technology. At 4 Gb/s the measured clock-phase-margin (CPM) is about 120 degrees, related to an ideal CPM of 180 degrees. Differential input sensitivity at 4 Gb/s is less than 150 mV.