A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-/spl mu/m CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3/spl times/ oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of /spl sim/3/spl times/3 mm/sup 2/.