The Gate-to-drain Overlap Effects on the Hot-carrier Induced Degradation of LDD P-channel MOSFET's

The gate-to-drain overlap effects on the hot carrier induced degradation of submicron LDD p-MOSFET's are investigated for the first time. Experimental results from three different structures, namely: 1) the reentrant poly gate, 2) the graded-gate-oxide and 3) the well overlapped gate and drain, are presented. We found that the weak overlap of an p-MOSFET improves the hot carrier immunity which is in sharp contrast to the n-MOSFET case.