Effects of technological and geometrical parameters of a tri-gate MOSFET fabricated in a bulk technology

We have investigated, by TCAD simulations, a tri-gate MOSFET fabricated in a bulk CMOS technology. By biasing both lateral-gates with the same voltage, this device is operated as a surface-gate transistor and a lateral one in parallel connection. We observe two different thresholds and a non-standard behavior of the lateral MOS due to source-drain doping profiles. This proposed device with multi-gate controllability may find many analog and digital applications. With the use of a mobility model, simulated results are compared with measured characteristics of the device. Effects of technological and geometrical parameters are identified and evaluated to allow performance optimization.