Modular Multiplication for Public Key Cryptography on FPGAs

All public key cryptosystems, though being highly secure, have a common drawback: They require heavy computational effort. This is due to the reliance on modular multiplication of large operands (1024 bits or higher). The same problem arises in data encryption/decryption and digital signature schemes. Examples of such cryptosystems are RSA, DSA, and ECC. Now considering embedded platforms for applications of smart cards and smart tokens, the overall time performance of the cipher system becomes very slow. This refers to the limited computational power of the embedded processors. This paper introduces an enhanced architecture for computing the modular multiplication of large operands. The proposed design can act as a co-processor for embedded general purpose CPUs. The proposed design is compared with three previous architectures depending on carry save adders and look up tables, and scoring 69 MHz of maximum frequency. Look up tables should be loaded with a set of pre-computed values. Our proposed architecture replaces both look up tables and pre-computations with an enhanced version of sign detection techniques. Considering 1024 bits architectures, the proposed design scored a maximum frequency of 181 MHz. It also has a better overall absolute time for a single operation.