Design of a 2.5Gbps Clock-Data Recovery circuit in 0.18um standard CMOS process

A 2.5 Gbps clock-data recovery (CDR) circuit is designed in 0.18 um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5 GHz by SONET OC-48 while the CMU loop runs at 625 MHz.The power consumption is 25 mW. The jitter bandwidth is 5.6 MHz. The peaking is 2.67 dB. The VCO gain is 163 MHz/V with a tuning range of 390 MHz. The output data and clock amplitude is 500 mV SEPP (single-ended peak to peak). Random jitter is 0.1 mUI rms and the output data ISI is 10 mUI.