A 64-bit, 2.4 GHz adder with SE detection capabilities employing time redundancy

The effect of single event transient is examined in a 64-bit logarithmic adder. Pseudo-static logic (PSL) is proposed to be an area efficient logic choice for time redundant circuit design. The proposed adder is capable of detecting 81% of the errors working at 2.4 GHz consuming 42mW of power. The detection capability comes at the expense of 19% power penalty and negligible area overhead. The results show that soft error detection can be achieved at low cost.