CMOS DLLBased 2V 3.2ps Jitter 1GHz Clock Synthesizer and TemperatureCompensated Tunable Oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter oC 3.1 ps was measured for a 1.6-GHzoutput. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from o°C to 85 °C. The circuits were fabricated on a generic 0.5-µm digital CMOS process.